1. Field of the Invention
The present invention generally relates to integrated circuit structures and methods of fabrication thereof and, more particularly, to the formation of high-value capacitors within small areas of an integrated circuit device or wafer and isolation structures of reduced size.
2. Description of the Prior Art
The increases in integration density achieved in integrated circuits in recent years have generally been accompanied by improvements in performance of the electronic devices formed therein and the integrated circuit devices, themselves, resulting from the reduced propagation times of signals over the distances between more closely packed devices. Substantial reductions in the cost of each electronic device therein has also been achieved since many more devices can be simultaneously formed than in the past even though newly developed and highly sophisticated techniques are often required for device fabrication.
However, the physical laws which govern the electrical properties of electronic devices limit the sizes to which some types of electronic devices can be scaled. Specifically, the capacitance of a charge storage structure is a well-known function of the area of spaced conductors, the spacing between the spaced conductors and the dielectric constant of material interposed between the spaced conductors. While newer designs and high-performance circuits have reduced the amount of charge which must be stored at a given voltage in, for example, a memory cell, and materials having increased dielectric constants and recent increases in resolution of lithographic processes have allowed some reductions in the physical size required for an integrated circuit capacitor for a given application, most increases in integration density have derived from the development of so-called trench capacitors which are formed vertically within a substrate and thus have a much reduced "footprint" on the surface of the substrate.
The geometry and orientation of trench capacitors require etching and deposition processes which are of increased expense due to the depth of trench required to obtain desired capacitance values. Specifically, since the trenches formed are generally of high aspect ratio (very deep in comparison with the width; narrowness of which is limited by the resolution of currently available lithographic exposure processes), etching and filling of trenches requires the corresponding process steps to be extended in duration. The duration of these processes, of course, carries the economic cost of operating expensive reactor apparatus as well as a fraction of the cost of the reactor apparatus and maintenance thereof which must be amortized over the number of integrated circuits fabricated, as well as the cost of power, chemical materials and the like which are required for and consumed by the process. For example, etch rates during reactive ion etching processes suitable for trench capacitors at the present state of the art in commercial processes are less than 1.0 .mu.m per minute and trench depths on the order of 10.0 .mu.m or more are commonly specified in current integrated circuit designs for trench capacitors and isolation structures. Filling trenches with a dielectric of suitably high dielectric constant usually proceeds even more slowly even though the time required to fill a trench scales with trench width. (That is, there is a trade-off between the capacitor "footprint" and the time required for filling the trench. Extremely narrow trenches with steep sidewalls needed for high integration density thus require process times which are very long.) Further, the filling of narrow, high aspect ratio features is difficult and manufacturing yields are often reduced or device reliability compromised by the closing of the top of the trench during deposition, resulting in the formation of voids within the trench. These voids can cause crystal dislocations and other defects which increase leakage and reduce breakdown voltage of the devices formed.
Since there is an inherent limit to the resolution of lithographic processes and narrowness of trench width has been limited to the minimum feature size which can be resolved in lithographic processes, there has been no solution to reduction of time required for filling of trenches consistent with high manufacturing yields and high integration density. Further, since trench width is limited to the minimum feature size, it has not been possible to reduce trench depth without causing a proportionate decrease in capacitance. Therefore, there has been no solution to the reduction of time required for the etching process at a given minimum size of capacitor "footprint" on the substrate. For example, while it is trivially true that process times could be halved by providing two "half-depth" trenches for each capacitor and some marginal improvement in manufacturing yield might be expected when shallower trenches were filled, the footprint required for developing a given capacitance value at a given feature size would be at least doubled, in view of the spacing required between features. Additionally, circuit layout would be complicated since trench capacitors are often formed in pairs (although each trench capacitor is individually accessible) to increase integration density. Therefore, the number of individually accessible capacitors which could be formed on a given chip or wafer would be at least halved and there would be no net benefit in cost per capacitor for the required processing. On the contrary, the cost impact would be an increase in the cost per capacitor since the number of wafers which can be simultaneously processed in a reactor apparatus is limited and therefore the cost of amortization of the reactor apparatus and maintenance thereof over a given number of wafers would be more than effectively doubled.
Because of these limitations on device fabrication techniques and the resulting geometry of the devices so formed, most major developments in improvement of capacitor value increase or size reduction have been due to metallurgical processes such as the development of hemispherical grain silicon which effectively increases the area of conductors in the capacitor. Improvements in capacitance value/size reduction on the order of 40% have been achieved in this manner. Otherwise, most improvements have been relatively marginal and some improvements which result in improvements in capacitance value/size reduction on the order of 5% to 10% are generally regarded in the art as being highly significant, indeed.